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19-2586; Rev 0; 10/02
3mm x 3m CSP
m
5mm x 5m QFN
m
Smallest TEC Power Drivers for Optical Modules
General Description Features
o Circuit Footprint of 0.31in2 o Low-Profile Design o On-Chip Power MOSFETs o High-Efficiency Switch-Mode Design o Ripple Cancellation for Low Noise o Direct Current Control Prevents TEC Current Surges o 5% Accurate Adjustable Heating/Cooling Current Limits o 2% Accurate TEC Voltage Limit o No Dead Zone or Hunting at Low Output Current o ITEC Monitors TEC Current o 1% Accurate Voltage Reference o Switching Frequency Up to 1MHz o Synchronization (MAX8521)
EVALUATION KIT AVAILABLE
MAX8520/MAX8521
The MAX8520/MAX8521 are designed to drive thermoelectric coolers (TECs) in space-constrained optical modules. Both devices deliver 1.5A output current and control the TEC current to eliminate harmful current surges. On-chip FETs minimize external components and high switching frequency reduces the size of external components. The MAX8520 and MAX8521 operate from a single supply and bias the TEC between the outputs of two synchronous buck regulators. This operation allows for temperature control without "dead zones" or other nonlinearities at low current. This arrangement ensures that the control system does not hunt when the set point is very close to the natural operating point, requiring a small amount of heating or cooling. An analog control signal precisely sets the TEC current. Both devices feature accurate, individually adjustable heating current limit and cooling current limit, along with maximum TEC voltage limit to improve the reliability of optical modules. An analog output signal monitors the TEC current. A unique ripple cancellation scheme helps reduce noise. The MAX8520 is available in a 5mm x 5mm thin QFN package and its switching frequency is adjustable up to 1MHz through an external resistor. The MAX8521 is also available in a 5mm x 5mm thin QFN, as well as a spacesaving 3mm x 3mm UCSPTM, with a pin-selectable switching frequency of 500kHz or 1MHz.
Ordering Information
PART MAX8520ETP MAX8521EBX MAX8521ETP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 Thin QFN 5mm x 5mm 36 UCSP 3mm x 3mm 20 Thin QFN 5mm x 5mm
Applications
SFF/SFP Modules Fiber-Optic Laser Modules Fiber-Optic Network Equipment ATE Biotech Lab Equipment
Typical Operating Circuit
INPUT 3V TO 5.5V VDD PVDD FREQ ON OFF TEC CURRENT MONITOR CURRENTCONTROL SIGNAL SHDN ITEC MAX8521 CTLI COMP REF GND PGND2 OS1 OS2 LX2 TEC OUTPUT ITEC = 1.5A CS LX1 PGND1
Pin Configurations appear at end of data sheet.
ANALOG /DIGITAL TEMPERATURE CONTROL
UCSP is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V SHDN, MAXV, MAXIP, MAXIN, CTLI to GND .........................................................-0.3V to +6V COMP, FREQ, OS1, OS2, CS, REF, ITEC to GND...........................................-0.3V to (VDD + 0.3V) PVDD1, PVDD2 to GND...............................-0.3V to (VDD + 0.3V) PVDD1, PVDD2 to VDD ...........................................-0.3V to +0.3V PGND1, PGND2 to GND .......................................-0.3V to +0.3V COMP, REF, ITEC Short to GND ...................................Indefinite LX Current (Note 1) ........................................2.25A LX Current Continuous Power Dissipation (TA = +70C) 20-Pin 5mm x 5mm x 0.9mm QFN (derate 20.8mW/C above +70C) (Note 2)...................................................1.67W 3mm x 3mm UCSP (derate 22mW/C above +70C).................................................................1.75W Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to exceed the IC's package power dissipation limits. Note 2: Solder underside metal slug to PC board ground plane.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = 0C to +85C, unless otherwise noted. Typical values at TA = +25C.)
PARAMETER Input Supply Range Maximum TEC Current Reference Voltage Reference Load Regulation MAXIP/MAXIN Threshold Accuracy VREF VREF VDD = 3V to 5.5V, IREF = 150A VDD = 3V to 5V, IREF = 10A to 1mA VDD = 5V VDD = 3V NFET On-Resistance PFET On-Resistance NFET Leakage PFET Leakage RDS(ON-N) RDS(ON-P) ILEAK(N) ILEAK(P) VDD = 5V, I = 0.2A VDD = 3V, I = 0.2A VDD = 5V, I = 0.2A VDD = 3V, I = 0.2A VLX = VDD = 5V, TA = +25C VLX = VDD = 5V, TA = +85C VLX = 0, TA = +25C VLX = 0, TA = +85C VCOMP = VREF = 1.500V, VDD = 5V VCOMP = VREF = 1.500V, VDD = 3.3V 500kHz mode 1MHz mode 500kHz mode 1MHz mode VMAXI_ = VREF VMAXI_ = VREF/3 VMAXI_ = VREF VMAXI_ = VREF/3 140 40 143 45 SYMBOL VDD CONDITIONS MIN 3.0 1.5 1.485 1.5 1.2 150 50 150 50 0.09 0.11 0.14 0.17 0.03 0.3 0.03 0.3 11 16 8 11 2 +165 2.50 2.40 2.65 2.55 2.80 2.70 14 21 11 14 3 mA C V mA 4 1.515 5.0 160 60 155 55 0.14 0.16 0.23 0.30 4 A A mV TYP MAX 5.5 UNITS V A V mV
No-Load Supply Current
IDD(NO
LOAD)
Shutdown Supply Current Thermal Shutdown UVLO Threshold
IDD-SD
SHDN = GND, VDD = 5V (Note 4) VDD rising VDD falling
TSHUTDOWN Hysteresis = 15C VUVLO
2
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Smallest TEC Power Drivers for Optical Modules
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = 0C to +85C, unless otherwise noted. Typical values at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MAX8521, FREQ= VDD, VDD = 3V to 5V MAX8521, FREQ= 0, VDD = 3V to 5V Internal Oscillator Switching Frequency fSW-INT MAX8520, REXT = 60k, VDD = 5V MAX8520, REXT = 60k, VDD = 3V MAX8520, REXT = 150k, VDD = 5V MAX8520, REXT = 150k, VDD = 3V External Sync Frequency Range LX_ Duty Cycle OS1, OS2, CS Input Current SHDN, FREQ Input Current SHDN, FREQ Input Low Voltage SHDN, FREQ Input High Voltage IOS1, IOS2, ICS ISHDN, IFREQ VIL VIH 25% < duty cycle <75% (MAX8521 only) (Note 5) 0 or VDD 0 or VDD, FREQ applicable for the MAX8521 only VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only VMAXV = VREF x 0.67, VOS1 to VOS2 = 4V, VDD = 5V VMAXV = VREF x 0.33, VOS1 to VOS2 = 2V, VDD = 3V IMAXV-BIAS, IMAXI_-BIAS ACTLI RCTLI gm VOS1 to VCS = 100mV, VOS1 = VDD/2 VMAXV = VMAXI_ = 0.1V or 1.5V VCTLI = 0.5V to 2.5V (Note 6) 1M terminated at REF VDD x 0.75 -2 -3 +2 +3 MIN 0.8 0.4 0.8 0.76 0.4 0.36 0.7 0 -100 -5 TYP 1 0.5 1 0.93 0.5 0.46 MAX 1.2 0.6 1.2 1.10 0.6 0.56 1.2 100 +100 +5 VDD x 0.25 MHz % A A V V % % MHz UNITS
MAX8520/MAX8521
MAXV Threshold Accuracy
MAXV, MAXI_ Input Bias Current CTLI Gain CTLI Input Resistance Error-Amp Transconductance VITEC Accuracy
-0.1 9.5 0.5 50 -10 10 1 100
+0.1 10.5 2.0 160 +10
A V/V M S %
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3
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
ELECTRICAL CHARACTERISTICS
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = -40C to +85C, unless otherwise noted.) (Note 7)
PARAMETER Input Supply Range Maximum TEC Current Reference Voltage Reference Load Regulation VREF VREF VDD = 3V to 5.5V, IREF = 150A VDD = 3V to 5V, IREF = 10A to 1mA VDD = 5V VDD = 3V NFET On-Resistance PFET On-Resistance RDS(ON-N) RDS(ON-P) VDD = 5V, I = 0.2A VDD = 3V, I = 0.2A VDD = 5V, I = 0.2A VDD = 3V, I = 0.2A VCOMP = VREF = 1.500V, VDD = 5V VCOMP = VREF = 1.500V, VDD = 3.3V VDD rising VDD falling MAX8521, FREQ = VDD, VDD = 3V to 5V MAX8521, FREQ = 0, VDD = 3V to 5V Internal Oscillator Switching Frequency fSW-INT MAX8520, REXT = 60k, VDD = 5V MAX8520, REXT = 60k, VDD = 3V MAX8520, REXT = 150k, VDD = 5V MAX8520, REXT = 150k, VDD = 3V External Sync Frequency Range LX_ Duty Cycle OS1, OS2, CS Input Current SHDN, FREQ Input Current SHDN, FREQ Input Low Voltage SHDN, FREQ Input High Voltage 25% < duty cycle <75% (MAX8521 only) (Note 5) IOS1, IOS2, 0 or VDD ICS ISHDN, IFREQ VIL VIH 0 or VDD, FREQ applicable for the MAX8521 only VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only VDD = 3V to 5.5V, FREQ applicable for the MAX8521 only VDD x 0.75 500kHz mode 1MHz mode VMAXI_ = VREF VMAXI_ = VREF/3 VMAXI_ = VREF VMAXI_ = VREF/3 140 40 143 45 SYMBOL VDD CONDITIONS MIN 3.0 1.5 1.480 1.515 5 160 60 155 55 0.14 0.16 0.23 0.30 14 21 11 14 3 2.50 2.40 0.8 0.4 0.8 0.76 0.4 0.36 0.7 0 -100 -5 2.80 2.70 1.2 0.6 1.2 1.10 0.6 0.56 1.2 100 +100 +5 VDD x 0.25 MHz % A A V V MHz mV MAX 5.5 UNITS V A V mV
MAXIP/MAXIN Threshold Accuracy
No-Load Supply Current
IDD(NO
LOAD)
Shutdown Supply Current UVLO Threshold
IDD-SD VUVLO
500kHz mode 1MHz mode SHDN = GND, VDD = 5V (Note 4)
mA
mA V
4
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Smallest TEC Power Drivers for Optical Modules
ELECTRICAL CHARACTERISTICS (continued)
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA = -40C to +85C, unless otherwise noted.) (Note 7)
PARAMETER SYMBOL CONDITIONS VMAXV = VREF x 0.67, VOS1 to VOS2 = 4V, VDD = 5V VMAXV = VREF x 0.33, VOS1 to VOS2 = 2V, VDD = 3V IMAXVBIAS, IMAXI_-BIAS CTLI Gain CTLI Input Resistance Error-Amp Transconductance VITEC Accuracy ACTLI RCTLI gm VOS1 to VCS = 100mV, VOS1 = VDD/2 VCTLI = 0.5V to 2.5V (Note 6) 1M terminated at REF 9.5 0.5 50 -10 10.5 2.0 160 +10 V/V M S % VMAXV = VMAXI_ = 0.1V or 1.5V MIN -2 -3 MAX +2 +3 UNITS % %
MAX8520/MAX8521
MAXV Threshold Accuracy
MAXV, MAXI_ Input Bias Current
-0.1
+0.1
A
Note 3: Note 4: Note 5: Note 6:
Enter 1MHz mode by tying a 60k resistor from FREQ to ground for the MAX8520, and tying FREQ to VDD for the MAX8521. Includes PFET leakage. Duty-cycle specification is guaranteed by design and not production tested. CTLI Gain is defined as:
ACTLI =
VCTLI ( VOS1 - VCS )
Note 7: Specifications to -40C are guaranteed by design and not production tested.
Typical Operating Characteristics
(VDD = 5V, circuit of Figure 1, TA = +25C, unless otherwise noted)
EFFICIENCY vs. TEC CURRENT (VDD = 5V, RTEC = 2)
MAX8520/21 toc01
EFFICIENCY vs. TEC CURRENT (VDD = 3.3V, RTEC = 1.3)
80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 FREQ = 500kHz FREQ = 1MHz
MAX8520/21 toc02
COMMON-MODE OUTPUT VOLTAGE RIPPLE
MAX8520/21 toc03
90 80 70 FREQ = 1MHz EFFICIENCY (%) 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 FREQ = 500kHz
90
C2 = C7 = 1F VOS2 20mV/div AC-COUPLED
VOS1 20mV/div AC-COUPLED ITEC = 1A 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 400ns/div
1.6
TEC CURENT (A)
TEC CURRENT (A)
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5
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25C, unless otherwise noted)
DIFFERENTIAL OUTPUT VOLTAGE RIPPLE
MAX8520/21 toc04
VDD RIPPLE
MAX8520/21 toc05
TEC CURRENT RIPPLE
MAX8520/21 toc06
C2 = C7 = 1F
1.5A VDD 20mV/div AC-COUPLED
VOS2 - VOS1 1mV/div AC-COUPLED
10mA/div AC-COUPLED
ITEC = 1A
ITEC = 1A
0A
400ns/div
400ns/div
400ns/div
TEC CURRENT vs. CTLI VOLTAGE
MAX8520/21 toc07
ZERO-CROSSING TEC CURRENT
MAX8520/21 toc08
VITEC vs. TEC CURRENT
MAX8520/21 toc09
3.0 VCTLI I00mV/div VITEC (V) 1.5V 2.5 2.0 1.5 1.0
VCTLI 1V/div
0V
0A ITEC 1A/div 0A ITEC 100mA/div 1ms/div 0.5 0 20ms/div -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 TEC CURRENT (A)
ITEC vs. AMBIENT TEMPERATURE
MAX8520/21 toc10
SWITCHING FREQUENCY vs. TEMPERATURE
FREQ = 1MHz 1000 SWITCHING FREQUENCY (kHz) 900 800 700 600 FREQ = 500kHz 500 400 VCTLI = 1.5V RTEC = 1
MAX8520/21 toc11
0.520 0.510 TEC CURRENT (A) 0.500 0.490 0.480 0.470 0.460 0.450 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (C) FREQ = 1MHz VCTLI = 2V RTEC = 1
1100
-40
-20
0
20
40
60
80
TEMPERATURE (C)
6
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Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25C unless otherwise noted)
SWITCHING FREQUENCY CHANGE vs. VDD
MAX8520/21 toc12
SWITCHING FREQUENCY vs. REXT
MAX8520/21 toc13
REFERENCE VOLTAGE CHANGE vs. VDD
REFERENCE VOLTAGE CHANGE (mV) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 REF SOURCING 150A
MAX8520/21 toc14
1200 SWITCHING FREQUENCY CHANGE (kHz) FREQ = 1MHz 1000 800 600 400 200 0 3.0 3.5 4.0 4.5 5.0 FREQ = 500kHz
1100 1000 SWITCHING FREQUENCY (kHz) 900 800 VDD = 5V 700 600 500 400 VDD = 3.3V
0.6
5.5
60
80
100
120
140
160
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
REXT (k)
VDD (V)
REFERENCE VOLTAGE CHANGE vs. TEMPERATURE
REFERENCE VOLTAGE CHANGE (mV) 4 3 2 1 0 -1 -2 -3 -4 -5 -40 -20 0 20 40 60 80 TEMPERATURE (C) -12 0 REF SOURCING 150A
MAX8520/21 toc15
REFERENCE VOLTAGE CHANGE vs. LOAD CURRENT
MAX8520/21 toc16
STARTUP AND SHUTDOWN WAVEFORMS
MAX8520/21 toc17
5 REFERENCE VOLTAGE CHANGE (mV)
0 -2 -4 -6 -8 -10
VSHDN 5V/div 0V IDD 200mA/div 0mA
ITEC 500mA/div 0mA
0.2
0.4
0.6
0.8
1.0
200s/div
LOAD CURRENT (mA)
CTLI STEP RESPONSE
MAX8520/21 toc18
VDD STEP RESPONSE
MAX8520/21 toc19
VCTLI 1V/div 1.5V
VDD 2V/div
0V
0A ITEC 1A/div 1ms 10ms/div
1A ITEC 10mA/div
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7
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25C unless otherwise noted)
THERMAL STABILITY, COOLING MODE
MAX8520/21 toc20
THERMAL STABILITY, ROOM TEMPERATURE
MAX8520/21 toc21
THERMAL STABILITY, HEATING MODE
MAX8520/21 toc22
TEMPERATURE 0.001C/div
TEMPERATURE 0.001C/div
TEMPERATURE 0.001C/div
TTEC = +25C TA = +45C 4s/div
TTEC = +25C TA = +25C 4s/div
TTEC = +25C TA = +5C 4s/div
Pin Description
PIN QFN 1 2 3 4 5 UCSP E1, E2 D1, D2, D3 C1 C2 B1 NAME LX1 PGND1 SHDN COMP ITEC FUNCTION Inductor Connection. LX1 is high-impedance in shutdown. Power Ground 1. Internal synchronous-rectifier ground connection. Connect all PGND pins together at power ground plane. Shutdown Control Input. Pull SHDN low to turn off PWM control and ITEC output. Current-Control Loop Compensation. Refer to the Compensation Capacitor section. TEC Current-Monitor Output. The ITEC output voltage is a function of the voltage across the TEC current-sense resistor. VITEC = VREF + 8 (VOS - VCS). Keep capacitance on ITEC <150pF. Maximum Negative TEC Current. Connect MAXIN to REF to set default negative current limit to -150mV/RSENSE. To lower this current limit, connect MAXIN to a resistor divider network from REF to GND. The current limit will then be equal to -(VMAXIN/VREF) x (150mV/RSENSE). Maximum Positive TEC Current. Connect MAXIP to REF to set default positive current limit to 150mV/RSENSE. To lower this current limit, connect MAXIP to a resistor divider network from REF to GND. The current limit will then be equal to (VMAXIP/VREF) x (150mV/RSENSE). Maximum Bipolar TEC Voltage. Connect MAXV to REF to set default maximum TEC voltage to VDD. To lower this limit, connect MAXV to a resistor-divider network from REF to GND. The maximum TEC voltage is equal to 4 x VMAXV or VDD, whichever is lower. 1.50V Reference Output. Bypass REF to GND with a 0. 1F ceramic capacitor.
6
A1
MAXIN
7
A2
MAXIP
8 9
A3 A4
MAXV REF
8
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Smallest TEC Power Drivers for Optical Modules
Pin Description (continued)
PIN QFN UCSP NAME FUNCTION TEC Current-Control Input. Sets TEC current. Center point is 1.50V (no TEC current). The current is given by: ITEC = (VOS1 - VCS) / RSENSE = (VCTLI - 1.50) / (10 x RSENSE). When (VCTLI - VREF) > 0, then VOS2 > VOS1 > VCS. Analog Ground. Start connect to PGND at underside exposed pad for QFN package. Analog Supply Voltage Input. Bypass VDD to GND with a 1F ceramic capacitor. For MAX8520: Analog FREQ Set Pin (see the Switching Frequency section). 13 C5 FREQ For MAX8521: Digital FREQ Selection Pin. Tie to VDD for 1MHz operation, tie to GND for 500kHz operation. The PWM oscillator can synchronize to FREQ by switching at FREQ between 700kHz and 1.2MHz. Power Ground 2. Internal synchronous rectifier ground connection. Connect all PGND pins together at the power ground plane. Inductor Connection. LX2 is high impedance in shutdown. Power Input 2. Connect all PVDD inputs together at the VDD power plane. Current-Sense Input. The current through the TEC is monitored between CS and OS1. The maximum TEC current is given by 150mV/RSENSE and is bipolar. Output Sense 2. OS2 senses one side of the differential TEC voltage. OS2 is a sense point, not a power output. OS2 discharges to ground in shutdown. Output Sense 1. OS1 senses one side of the differential TEC voltage. OS1 is a sense point, not a power output. OS1 discharges to ground in shutdown. Power Input 1. Connect all PVDD inputs together at the VDD power plane. Ground. Additional ground pads aid in heat dissipation. Short to either GND or PGND plane. No Connect. Connect no-connect pads to GND2 to aid in heat dissipation.
MAX8520/MAX8521
10
A5
CTLI
11 12
A6 B6
GND VDD
14 15 16 17 18 19 20
D4, D5, D6 E5, E6 F5, F6 F4 C6 F3 F1, F2 B2, B5, C3, C4 B3, B4 E3, E4
PGND2 LX2 PVDD2 CS OS2 OS1 PVDD1 GND2 N.C.
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9
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
Detailed Description
The MAX8520/MAX8521 TEC drivers consist of two switching buck regulators that operate together to directly control the TEC current. This configuration creates a differential voltage across the TEC, allowing bidirectional TEC current for controlled cooling and heating. Controlled cooling and heating allow accurate TEC temperature control to within 0.01C. The voltage at CTLI directly sets the TEC current. An external thermal- control loop is typically used to drive CTLI. Figures 1 and 2 show examples of the thermal control-loop circuit.
Table 1. TEC Connection for Figure 1
TEC CONNECTION Heating mode Cooling mode THERMISTOR PTC NTC
Table 2. TEC Connection for Figure 2
TEC CONNECTION Heating mode Cooling mode THERMISTOR NTC PTC
Ripple Cancellation
Switching regulators like those used in the MAX8520/ MAX8521 inherently create ripple voltage on the output. The dual regulators in the MAX8520/MAX8521 switch in phase and provide complementary in-phase duty cycles so ripple waveforms at the TEC are greatly reduced. This feature suppresses ripple currents and electrical noise at the TEC to prevent interference with the laser diode.
Current Monitor Output
ITEC provides a voltage output proportional to the TEC current (ITEC). See the Functional Diagram for more details: VITEC = 1.5V +(8 (VOS1-VCS))
Reference Output
The MAX8520/MAX8521 include an on-chip voltage reference. The 1.50V reference is accurate to 1% over temperature. Bypass REF with 0.1F to GND. REF can be used to bias an external thermistor for temperature sensing as shown in Figures 1 and 2.
Switching Frequency
For the MAX8521, FREQ sets the switching frequency of the internal oscillator. With FREQ = GND, the oscillator frequency is set to 500kHz. The oscillator frequency is 1MHz when FREQ = VDD. For the MAX8520, connect a resistor (REXT in Figure 2) from FREQ to GND. Choose REXT = 60k for 1MHz operation, and REXT = 150k for 500kHz operation. For any intermediary frequency between 500kHz and 1MHz, use the following equation to find the value of REXT value needed for VDD = 5V: 1 1 REXT = 90 x - fs 3 where REXT is the resistance given in k, and fs is the desired frequency given in MHz. Note that for VDD < 5V, the frequency is reduced slightly, to the extent of about 7% when VDD reaches 3V. This should be taken into consideration when selecting the value for REXT at a known supply voltage.
Thermal and Fault-Current Protection
The MAX8520/MAX8521 provide fault-current protection in either FET by turning off both high-side and low-side FETs when the peak current exceeds 3A in either FET. In addition, thermal-overload protection limits the total power dissipation in the chip. When the device's die junction temperature exceeds +165C, an on-chip thermal sensor shuts down the device. The thermal sensor turns the device on again after the junction temperature cools down by 15C.
Design Procedures
Duty-Cycle Range Selection
By design, the MAX8520/MAX8521 are capable of operating from 0% to 100% duty cycle, allowing both LX outputs to enter dropout. However, as the LX pulse width narrows, accurate duty-cycle control becomes difficult. This can result in a low-frequency noise appearing at the TEC output (typically in the 20kHz to 50kHz range). While this noise is typically filtered out by the low thermal-loop bandwidth, for best results, operate the PWM with a pulse width greater than 200ns. For a 500kHz application, the recommended duty-cycle range is from 10% to 90%. For a 1MHz application, it is from 20% to 80%.
Voltage and Current-Limit Setting
Both the MAX8520 and MAX8521 provide control of the maximum differential TEC voltage. Applying a voltage to MAXV limits the maximum voltage across the TEC. The voltage at MAXIP and MAXIN sets the maximum positive and negative current through the TEC. These current limits can be independently controlled.
10
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Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
VDD VDD C1 1F LX1 CS RSENSE 0.09 PVDD1 C3 1F PGND1 U1 PVDD2 C4 1F PGND2 REF C6 0.1F MAXIP MAXIN 49.9k MAXV 100k CTLI GND FREQ ITEC ON SHDN OFF LX2 COMP C8 0.1F C7 1F VDD MAX8521 OS2 L2 4.7F OS1 RTHER C5 10F C2 1F R2 L1 4.7F REF
0.022F
10k 243k 10F
1F
U3A U2
MAX4475
510k TO U3B OUTPUT REF U4
MAX5144
MAX4477
VDD
100k
10k
DAC INPUTS
U3B MAX4477
Figure 1. MAX8521 Typical Application Circuit
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11
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
VDD VDD C1 1F LX1 CS RSENSE 0.09 PVDD1 C3 1F PGND1
U1
L1 4.7F REF C2 1F R2
OS1 RTHER C5 10F
PVDD2 C4 1F PGND2 REF C6 0.1F MAXIP MAXIN 49.9k ITEC MAXV 100k SHDN CTLI GND OFF ON FREQ REXT 60k LX2 COMP C8 0.1F C7 1F MAX8520 OS2 L2 4.7F
0.022F
1k 243k 10F
10F
U2 MAX4238
50k
0.01F
REF
VDD
DAC INPUTS
U4 MAX5144
Figure 2. Typical Application Circuit for the MAX8520 with Reduced Op-Amp Count Configuration
12
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Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
3/4 VDD
1/4 VDD LX2 -1.2
REF CTLI 1 R R 0.5X gm CCOMP
COMP
1.2X
PWM 4X
RSENSE LX1 +1.2
REF 10X
CS OS1
Figure 3. Functional Diagram of the Current-Control Loop
Inductor Selection
The MAX8520/MAX8521 dual buck converters operate in phase and in complementary mode to drive the TEC differentially in a current-mode control scheme. At zero TEC current, the differential voltage is zero; hence, the outputs with respect to GND are equal to half of VDD. As the TEC current demand increases, one output goes up and the other goes down from the initial point of 0.5VDD by an amount equal to 0.5 VTEC (VTEC = ITEC RTEC). Therefore, the operating duty cycle of each buck converter depends on the operating I TEC and RTEC. Since inductor current calculations for heating and cooling are identical, but reverse in polarity, the calculations only need to be carried out for either one. For a given inductor and input voltage, the maximum inductor ripple current happens when the duty cycle is at 50%. Therefore, the inductor should be calculated at 50% duty cycle to find the maximum ripple current. The maximum desired ripple current of a typical standard buck converter is in the range of 20% to 40% of the maximum load. The higher the value of the inductor, the lower the ripple current. However, the size is physically larger. For the TEC driver, the thermal loop is inherently slow, so the inductor can be larger for lower ripple current for better noise and EMI performance. Picking an inductor to yield ripple current of 10% to 20% of the maximum TEC current is a good starting point.
Calculate the inductor value as follows: L=
LIR x I TEC(MAX) x fs
(0.25
x VDD )
where LIR is the selected inductor ripple-current ratio, ITEC(MAX) is the maximum TEC current, and fs is the switching frequency. As an example, for VDD = 3.3V, LIR = 12%, and fs = 1MHz, L = 4.58H. Even though each inductor ripple current is at its maximum at 50% duty cycle (zero TEC current), the ripple cancels differentially because each is equal and in phase.
Output Filter Capacitor Selection
Common-Mode Filter Capacitors
The common-mode filter capacitors (C2 and C7 of Figure 1) are used as filter capacitors to ground for each output. The output ripple voltage depends on the capacitance, the ESR of these capacitors, and the inductor ripple current. Ceramic capacitors are recommended for their low ESR and impedance at high frequency.
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13
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
The output common-mode ripple voltage can be calculated as follows: VRIPPLE(P-P) = LIR x ITEC(MAX) (ESR + 1/8 x C x fs) A 1F ceramic capacitor with ESR of 10m with LIR = 12% and ITEC(MAX) = 1.5A results in VRIPPLE(P-P) of 24.3mV. For size-constraint applications, the capacitor can be made smaller at the expense of higher ripple voltage. However, the capacitance must be high enough so that the LC resonant frequency is less than 1/5 the switching frequency: f= 1 2 LC bypassing may be needed to stabilize the input supply. In such cases, a low-ESR electrolytic or ceramic capacitor of 100F or more at VDD is sufficient.
Compensation Capacitor
A compensation capacitor is needed to ensure currentcontrol-loop stability (see Figure 3). Select the capacitor so that the unity-gain bandwidth of the current-control loop is less than or equal to 10% the resonant frequency of the output filter: g 24 x RSENSE CCOMP m x fBW 2(RSENSE x RTEC ) where: fBW = unity-gain bandwidth frequency, less than or equal to 10% the output filter resonant frequency gm = loop transconductance, typically 100A/V CCOMP = value of the compensation capacitor RTEC = TEC series resistance; use the minimum resistance value RSENSE = sense resistor
where f is the resonant frequency of the output filter.
Differential Mode Filter Capacitor
The differential-mode filter capacitor (C5 in Figure 1) is used to bypass differential ripple current through the TEC as the result of unequal duty cycle of each output. This happens when the TEC current is not at zero. As TEC current increases from zero, both outputs move away from the 50% duty-cycle point complementarily. The common-mode ripple decreases, but the differential ripple does not cancel perfectly, and there is a resulting differential ripple. The maximum value happens when one output is at 75% duty cycle and the other is at 25% duty cycle. At this operating point, the differential ripple is equal to 1/2 of the maximum common-mode ripple. The TEC ripple current determines the TEC performance, because the maximum temperature differential that can be created between the terminals of the TEC depends on the ratio of ripple current and DC current. The lower the ripple current, the closer to the ideal maximum. The differential-mode capacitor provides a low-impedance path for the ripple current to flow, so that the TEC ripple current is greatly reduced. The TEC ripple current can then be calculated as follows: ITEC(RIPPLE) = (0.5 x LIR x ITEC(MAX)) x (ZC5)/(RTEC + RSENSE + ZC5) where ZC5 is the impedance of C5 at twice the switching frequency, RTEC is the TEC equivalent resistance, and RSENSE is the current-sense resistor.
Setting Voltage and Current Limits
Certain TEC parameters must be considered to guarantee a robust design. These include maximum positive current, maximum negative current, and the maximum voltage allowed across the TEC. These limits should be used to set the MAXIP, MAXIN, and MAXV voltages. Setting Max Positive and Negative TEC Current MAXIP and MAXIN set the maximum positive and negative TEC currents, respectively. The default current limit is 150mV/RSENSE when MAXIP and MAXIN are connected to REF. To set maximum limits other than the defaults, connect a resistor-divider from REF to GND to set VMAXI_. Use resistors in the 10k to 100k range. VMAXI_ is related to ITEC by the following equations: VMAXIP = 10(ITECP(MAX) RSENSE) VMAXIN = 10(ITECN(MAX) RSENSE) where ITECP(MAX) is the maximum positive TEC current and ITECN(MAX) is the negative maximum TEC current. Positive TEC current occurs when CS is less than OS1: ITEC x RSENSE = OS1 - CS when ITEC > 0. ITEC RSENSE = CS - OS1 when ITEC < 0.
Decoupling Capacitor Selection
Decouple each power-supply input (V DD , PV DD 1, PVDD2) with a 1F ceramic capacitor close to the supply pins. In applications with long distances between the source supply and the MAX8520/MAX8521, additional
14
______________________________________________________________________________________
Smallest TEC Power Drivers for Optical Modules
Take care not to exceed the positive or negative current limit on the TEC. Refer to the manufacturer's data sheet for these limits.
Applications Information
The MAX8520/MAX8521 typically drive a TEC inside a thermal-control loop. TEC drive polarity and power are regulated based on temperature information read from a thermistor or other temperature-measuring device to maintain a stable control temperature. Temperature stability of 0.01C can be achieved with carefully selected external components. There are numerous ways to implement the thermal loop. Figures 1 and 2 show designs that employ precision op amps, along with a DAC or potentiometer to set the control temperature. The loop may also be implemented digitally, using a precision A/D to read the thermistor or other temperature sensor, a microcontroller to implement the control algorithm, and a DAC (or filtered-PWM signal) to send the appropriate signal to the MAX8520/MAX8521 CTLI input. Regardless of the form taken by the thermalcontrol circuitry, all designs are similar in that they read temperature, compare it to a set-point signal, and then send an error-correcting signal to the MAX8520/ MAX8521 that moves the temperature in the appropriate direction.
MAX8520/MAX8521
Setting Max TEC Voltage
Apply a voltage to the MAXV pin to control the maximum differential TEC voltage. MAXV can vary from 0 to REF. The voltage across the TEC is four times VMAXV and can be positive or negative: |VOS1 - VOS2| = 4 x VMAXV or VDD, whichever is lower Set VMAXV with a resistor-divider between REF and GND using resistors from 10k to 100k. VMAXV can vary from 0 to REF.
Control Inputs/Outputs
Output Current Control The voltage at CTLI directly sets the TEC current. CTLI is typically driven from the output of a temperature control loop. The transfer function relating current through the TEC (ITEC) and VCTLI is given by: ITEC = (VCTLI - VREF) / (10 RSENSE) where VREF is 1.50V and: ITEC = (VOS1 - VCS) / RSENSE CTLI is centered around REF (1.50V). ITEC is zero when CTLI = 1.50V. When VCTLI > 1.50V, the current flow is from OS2 to OS1. The voltages on the pins relate as follows: VOS2 > VOS1 > VCS The opposite applies when VCTLI < 1.50V current flows from OS1 to OS2: VOS2 < VOS1 < VCS Shutdown Control The MAX8520/MAX8521 can be placed in a power-saving shutdown mode by driving SHDN low. When the MAX8520/MAX8521 are shut down, the TEC is off (OS1 and OS2 decay to GND) and supply current is reduced to 2mA (typ). ITEC Output ITEC is a status output that provides a voltage proportional to the actual TEC current. VITEC = REF when TEC current is zero. The transfer function for the ITEC output is: VITEC = 1.50 + 8 (VOS1 - VCS) Use ITEC to monitor the cooling or heating current through the TEC. For stability, keep the load capacitance on ITEC to less than 150pF.
PC Board Layout and Routing
High switching frequencies and large peak currents make PC board layout a very important part of design. Good design minimizes excessive EMI and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Follow these guidelines for good PC board layout: 1) Place decoupling capacitors as close to the IC pins as possible. 2) Keep a separate power ground plane, which is connected to PGND1 and PGND2. PV DD 1, PV DD 2, PGND1, and PGND2 are noisy points. Connect decoupling capacitors from PVDDs to PGNDs as directly as possible. Output capacitors C2 and C7 returns are connected to PGND plane. 3) Connect a decoupling capacitor from VDD to GND. Connect GND to a signal ground plane (separate from the power ground plane above). Other VDD decoupling capacitors (such as the input capacitor) need to be connected to the PGND plane. 4) Connect GND and PGND_ pins together at a single point, as close as possible to the chip. 5) Keep the power loop, which consists of input capacitors, output inductors, and capacitors, as compact and small as possible.
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15
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
6) To ensure high DC loop gain and minimum loop error, keep the board layout adjacent to the negative input pin of the integrator (U2 in Figure1) clean and free of moisture. Any contamination or leakage current into this node can act to lower the DC gain of the integrator, which can degrade the accuracy of the thermal loop. If space is available, it can also be helpful to surround the negative input node of the integrator with a grounded guard ring. Refer to the MAX8520/MAX8521 evaluation kit for a PC board layout example.
Chip Information
TRANSISTOR COUNT: 3007 PROCESS: BiCMOS
Pin Configurations
20 PVDD1 19 OS1 18 OS2 17 CS
TOP VIEW
16 PVDD2
MAX8521
F5 F6 PVDD2 PVDD2 E6 LX2 E5 LX2 F4 CS E4 N.C. F3 OS1 E3 N.C. F2 F1 PVDD1 PVDD1 E2 LX1 E1 LX1
LX1 PGND1 SHDN COMP ITEC
1 2 3 4 5 10 6 7 8 9
15 14
LX2 PGND2 FREQ VDD GND
MAX8520/ MAX8521
13 12 11
D6 D5 D4 D3 D2 D1 PGND2 PGND2 PGND2 PGND1 PGND1 PGND1 C6 OS2 B6 VDD A6 GND C5 FREQ B5 GND2 A5 CTLI C4 GND2 B4 N.C. A4 REF C3 GND2 B3 N.C. A3 MAXV C2 C1 COMP SHDN B2 GND2 B1 ITEC
MAXIN
MAXIP
MAXV
CTLI
REF
A2 A1 MAXIP MAXIN
THIN QFN
UCSP
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Smallest TEC Power Drivers for Optical Modules
Functional Diagram
ON OFF SHDN REF REF FREQ (MAX8521) VDD PVDD1 MAXV MAX VTEC = VMAXV x 4 OR VDD LX1 MAXIP MAX ITEC = (VMAXIP/VREF) x (0.15V/RSENSE) MAX ITEC = (VMAXIN/VREF) x (0.15V/RSENSE) 3V TO 5.5V
MAX8520/MAX8521
MAXIN
PWM CONTROL AND GATE CONTROL
PGND1 CS RSENSE OS1
CS OS2 ITEC OS1 REF CTLI COMP LX2 PVDD2 VDD
GND FREQ (MAX8520)
MAX8520/ MAX8521
PGND2
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17
Smallest TEC Power Drivers for Optical Modules MAX8520/MAX8521
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
18
______________________________________________________________________________________
Smallest TEC Power Drivers for Optical Modules
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
36L,UCSP.EPS
MAX8520/MAX8521
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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